TNFG - uOMIC

Contents

This sheet shows the documentation for the rhomb uPmic. Preliminary version, use only for data updating or corrections.

Description

Rhomb uPMIC is a complete power management IC that enables to power the core processor, external memory and peripherals from a single-chip. A whole system power solution with automatic and user-configurable power-On sequence. A perfect solution for multiple applications.

Rhomb uPMIC contains 9 high efficient buck converters, 26 LDOs, RTC, 3-channel 32kHz clock output, backup battery charger, manual reset and shutdown inputs, reset output, input and output interrupts and UART serial interface to program individual regulator output voltages and on/off control. All for complete flexibility in a diminutive single-chip (11x11mm LGA package)

With its internal inductors for all bucks, Rhomb uPMIC helps to maximize power efficiency and battery life, supporting high levels of integration, reducing design complexity, minimizing motherboard space and lowering overall bill of materials.

Features

  • 9 High Efficiency Buck Converters
    • 6 x 1.5A Bucks: BUCK1, 5, 6, 7, 8 & 9
    • 2 x 5A Bucks: BUCK2 & 4
    • 1 x 2.5A Buck: BUCK3
    • BUCK2, 3 & 4 with DVS Function and programmable voltage from 0.6V to 3.7875V in 12.5mV step
    • BUCK1, 5, 6, 8 & 9 programmable voltage from 0.75V to 3.90V in 50mV step
    • BUCK7 always ON, 2.00V fix voltage
    • UART ON/OFF control for all Bucks
    • Digital ON/OFF control for BUCK1, 2, 3, 4, 8 & 9
    • Internal inductors for all bucks
  • 26 Linear Regulators with Green Mode
    • 1 x 450mA NMOS LDO
    • 1 x 300mA NMOS LDO
    • 4 x 150mA NMOS LDOs
    • 6 x 300mA PMOS LDOs
    • 14 x 150mA PMOS LDOs
    • Programmable voltage for all PMOS LDOs: from 0.8V to 3.95V in 50mV step
    • Programmable voltage for all NMOS LDOs: from 0.8V to 2.375V in 25mV step
    • Green Mode with 1uA typ for all LDOs
    • UART ON/OFF control for all LDOs
    • Digital ON/OFF control for LDO2, 6, 7, 8, 10, 11, 12, 14, 15, 16, 20, 21 & 22
    • Buffered 3-ch 32.768kHz Outputs with Low Jitter
  • Automatic power-Up sequence
  • RTC with backup battery charger and two alarms
  • Single button manual RESET and single button System SHUTDOWN
  • Power-On reset output
  • 1 x interrupt input, 1 x interrupt request output
  • 1 x external MOSFET control pin, 1 x 1-Wire port
  • 2 x GPIO/ADC pins
  • Small package, 144-pin 12x12mm LGA (0.8mm pitch)

Applications

  • Smartphones, tablets, netbooks.
  • Video game consoles, smart TV.
  • Industrial control.
  • Home automation.
  • Security/Energy management.

Power Summary

Power

Output

Voltage Range

(V)

Step
 (mV)
Load_Current

(mA)

Power

Input

ON/OFF

Control

LDO

Type

Note
BUCK1 0.75 ~ 3.90 50 1500 INB1 PWREN or UART -
BUCK2 0.6 ~ 3.7875 12.5 5000 INB2A

INB2B

DVS Function &

PWREN external enable/disable pin

BUCK3 2500 INB3
BUCK4 5000 INB4A

INB4B

BUCK5 0.75 ~ 3.90 50 1500 INB5 UART
BUCK6 150 INB6
BUCK7 2.00 - INB7 ALWAYS ON
BUCK8 0.75 ~ 3.90 50 INB8 ENB8 or UART ENB8, external enable/disable pin
BUCK9 INB9 ENB9 or UART ENB9, external enable/disable pin
LDO1 0.80 ~ 2.375 25 INL1 UART NDRV1
LDO2 450 INL7 PWREN or UART NDRV3
LDO3 0.80 ~ 1.85 50 300 internal UART PDRV2
LDO4 0.80 ~ 3.95 150 INL4 UART PDRV1
LDO5 0.80 ~ 3.95 INL2 UART
LDO6 0.80 ~ 2.375 25 INL1 PWREN or UART NDRV1
LDO7
LDO8 300 NDRV2
LDO9 0.80 ~ 1.85 50 150 internal UART PDRV1
LDO10 0.80 ~ 3.95 300 INL5 PWREN or UART PDRV2
LDO11 0.80 ~ 1.85 150 internal PDRV1
LDO12 0.80 ~ 3.95 INL4
LDO13 INL5 UART
LDO14 PWREN or UART
LDO15 0.80 ~ 2.375 25 INL1 NDRV1
LDO16 0.80 ~ 3.95 50 INL5 PDRV1
LDO17 300 INL2 UART PDRV2
LDO18 150 PDRV1
LDO19
LDO20 0.80 ~ 1.85 internal LDOEN or UART LDOEN external enable/disable pin
LDO21 0.80 ~ 3.95 300 INL4 PDRV2
LDO22 INL6
LDO23 UART
LDO24 150 INL4 PDRV1
LDO25 INL6
LDO26

Pin Description

PIN Nº PIN NAME PIN DESCRIPTION
BUCK CONVERTERS
BUCK1
INB1 Input terminal to Buck1 converter. Bypass with a 2.2uF to ground.
BUCK1 Output terminal from Buck1. Bypass with a 4.7uF to ground. Place the pin as close to the load as possible.
PGND1 Power ground for Buck1 converter.
BUCK2
INB2A Input terminal to first-phase of Buck2 converter. Bypass with a 10uF to ground.
INB2B Input terminal to second-phase of Buck2 converter. Bypass with a 10uF to ground.
BUCK2A Output terminal from Buck2. Bypass with a 22uF to ground. Place the pinas close to the load as possible.
BUCK2B Output terminal from Buck2. Bypass with a 22uF to ground. Place the pin as close to the load as possible.
SNS2P Sense + for Buck2. place the pin as close to the load as possible.
SNS2N Sense - for Buck2. place the pin as close to the load as possible.
PGND2A Power ground for the first-phase of Buck2.
PGND2B Power ground for the second-phase of Buck2.
BUCK3
INB3 Input terminal to Buck3 converter. Bypass with a 10uF to ground.
BUCK3 Output terminal from Buck3. Bypass with a 22uF to ground. Place the pin as close to the load as possible.
SNS3P Sense + for Buck3. place the pin as close to the load as possible.
SNS3N Sense - for Buck3. place the pin as close to the load as possible.
PGND3 Power ground for Buck3 converter.
BUCK4
INB4A Input terminal to first-phase of Buck4 converter. Bypass with a 10uF to ground.
INB4B Input terminal to second-phase of Buck4 converter. Bypass with a 10uF to ground.
BUCK4A Output terminal from Buck4. Bypass with a 22uF to ground. Place the pin as close to the load as possible.
BUCK4B Output terminal from Buck4. Bypass with a 22uF to ground. Place the pin as close to the load as possible.
SNS4P Sense + for Buck4. place the pin as close to the load as possible.
SNS4N Sense - for Buck4. place the pin as close to the load as possible.
PGND4A Power ground for the first-phase of Buck4.
PGND4B Power ground for the second-phase of Buck4.
BUCK5
INB5 Input terminal to Buck5 converter. Bypass with a 2.2uF to ground.
BUCK5 Output terminal from Buck5. Bypass with a 4.7uF to ground. Place the pin as close to the load as possible.
PGND5 Power ground for Buck5 converter.
BUCK6
INB6 Input terminal to Buck6 converter. Bypass with a 2.2uF to ground.
BUCK6 Output terminal from Buck6. Bypass with a 4.7uF to ground. Place the pin as close to the load as possible.
PGND6 Power ground for Buck6 converter.
BUCK7
INB7 Input terminal to Buck7 converter. Bypass with a 2.2uF to ground.
BUCK7 Output terminal from Buck7, 2.00V Always-On when not in shut-down mode. Bypass with a 4.7uF to ground. Place the pin as close to the load as possible.
PGND7 Power ground for Buck7 converter.
BUCK8
INB8 Input terminal to Buck8 converter. Bypass with a 2.2uF to ground.
BUCK8 Output terminal from Buck8. Bypass with a 4.7uF to ground. Place the pin as close to the load as possible.
ENB8 External enable/disable pin. Active-high to enable, it has a 800kΩ internal pull-down resistance to ground. If this pin is not used, leave it open.
PGND8 Power ground for Buck8 converter.
BUCK9
INB9 Input terminal to Buck9 converter. Bypass with a 2.2uF to ground.
BUCK9 Output terminal from Buck9. Bypass with a 4.7uF to ground. Place the pin as close to the load as possible.
ENB9 External enable/disable pin. Active-high to enable, it has a 800kΩ internal pull-down resistance to ground. If this pin is not used, leave it open.
PGND9 Power ground for Buck9 converter.
DVS INPUTS
DVS1 Dynamic Voltage Scalling logic input for BUCK2, 3, 4. For details, refer to the technical description on DVS section.
DVS2 Dynamic Voltage Scalling logic input for BUCK2, 3, 4. For details, refer to the technical description on DVS section.
DVS3 Dynamic Voltage Scalling logic input for BUCK2, 3, 4. For details, refer to the technical description on DVS section.
SELB2 Voltage selection logic input for BUCK2. Logic-high for no DVS, logic low for DVS enabled. For details, refer to the technical description.
SELB3 Voltage selection logic input for BUCK3. Logic-high for no DVS, logic low for DVS enabled. For details, refer to the technical description.
SELB4 Voltage selection logic input for BUCK4. Logic-high for no DVS, logic low for DVS enabled. For details, refer to the technical description.
LINEAR REGULATORS
INL1 Input to LDO1, 6, 7, 8, 15. Bypass with a 4.7uF to ground.
OUT1 150mA NMOS LDO1 OUTPUT. Bypass with a 1uF to ground.
OUT6 150mA NMOS LDO6 OUTPUT. Bypass with a 1uF to ground.
OUT7 150mA NMOS LDO7 OUTPUT. Bypass with a 1uF to ground.
OUT8 300mA NMOS LDO8 OUTPUT. Bypass with a 1uF to ground.
OUT15 150mA NMOS LDO15 OUTPUT. Bypass with a 1uF to ground.
INL2 Input to LDO5, 17, 18,19. Bypass with a 4.7uF to ground.
OUT5 150mA PMOS LDO5 OUTPUT. Bypass with a 1uF to ground.
OUT17 300mA PMOS LDO17 OUTPUT. Bypass with a 2.2uF to ground.
OUT18 150mA PMOS LDO18 OUTPUT. Bypass with a 1uF to ground.
OUT19 150mA PMOS LDO19 OUTPUT. Bypass with a 1uF to ground.
--- Internal input power supply to LDO3,9,11,20. Internally connected to BUCK7 (2.00V Always-On when not in shut-down mode)
OUT3 300mA PMOS LDO3 OUTPUT. Internal input power supply. Bypass with a 2.2uF to ground.
OUT9 150mA PMOS LDO9 OUTPUT. Internal input power supply. Bypass with a 1uF to ground.
OUT11 150mA PMOS LDO11 OUTPUT. Internal input power supply. Bypass with a 1uF to ground.
OUT20 150mA PMOS LDO20 OUTPUT. Internal input power supply. Bypass with a 1uF to ground.
INL4 Input to LDO4, 12, 21, 24. Bypass with a 4.7uF to ground.
OUT4 150mA PMOS LDO4 OUTPUT. Bypass with a 1uF to ground.
OUT12 150mA PMOS LDO12 OUTPUT. Bypass with a 1uF to ground.
OUT21 300mA PMOS LDO21 OUTPUT. Bypass with a 2.2uF to ground.
OUT24 150mA PMOS LDO24 OUTPUT. Bypass with a 1uF to ground.
INL5 Input to LDO10, 13, 14, 16. Bypass with a 4.7uF to ground.
OUT10 300mA PMOS LDO10 OUTPUT. Bypass with a 2.2uF to ground.
OUT13 150mA PMOS LDO13 OUTPUT. Bypass with a 1uF to ground.
OUT14 150mA PMOS LDO14 OUTPUT. Bypass with a 1uF to ground.
OUT16 150mA PMOS LDO16 OUTPUT. Bypass with a 1uF to ground.
INL6 Input to LDO22, 23, 25, 26. Bypass with a 4.7uF to ground.
OUT22 300mA PMOS LDO22 OUTPUT. Bypass with a 2.2uF to ground.
OUT23 300mA PMOS LDO23 OUTPUT. Bypass with a 2.2uF to ground.
OUT25 150mA PMOS LDO25 OUTPUT. Bypass with a 1uF to ground.
OUT26 150mA PMOS LDO26 OUTPUT. Bypass with a 1uF to ground.
INL7 Input to LDO2. Bypass with a 1uF to ground
OUT2 450mA NMOS LDO2 OUTPUT. Bypass with a 1uF to ground.
SUPPLY
VIN Main Supply input for internal circuitry. Bypass with a 1uF to GND.
GND Power ground for internal circuitry
GND Power ground for internal circuitry
GND Power ground for internal circuitry
GND Power ground for internal circuitry
GND Power ground for internal circuitry
GND Power ground for internal circuitry
GND Power ground for internal circuitry
GND Power ground for internal circuitry
ON/OFF POWER CONTROL and RESET
#PWRON External SYSTEM-ON control signal. Active-low with 70msec debounced time initiates the power-on sequence. This pin has an internal pull-up of 30k to internal 1V8. Once the system is ON this pin can be used as Manual Reset button with programmable debounce timer.
PWREN External enable/disable pin. Enable pin for certain BUCKs and LDOs (all enabled or disabled at a time). For the details, refer to the technical description
LDOEN External enable/disable pin. Active high to enable LDO20,21,22 (all three at the same time). A 800kΩ internal pull-down resistance to the ground
ENB8 External enable/disable pin. Active high to enable BUCK8. Active-high to enable, it has a 800kΩ internal pull-down resistance to ground. If this pin is not used, leave it open.
ENB9 External enable/disable pin. Active-high to enable, it has a 800kΩ internal pull-down resistance to ground. If this pin is not used, leave it open.
#SHTDN Manual system shutdown input. Active-low to generate manual shutdown process. This pin has an internal pull-up of 56k to internal 1V8. If this pin is not used, leave it open.
#RESET Manual system reset Input. Active-low to generate manual reset process. This pin has an internal pull-up of 30k to internal 1V8
#RSTOUT Reset output. Active-low with internal pull-up of 30k to internal 1V8 (it can be disabled by firmware). If this pin is not used, leave it open.
INPUT/OUTPUT
#INT Interrupt input. Active-low with internal pull-up of 30k to internal 1V8.
#IRQ Interrupt request output. Active-low with no internal pull-up.
SPLYCTRL External power supply controller. Connect this pin to the gate of an external MOSFET. For details, refer to the technical description.
GPIO0 General purpose digital input/output pin (interrupt available) or Analog input. For details, refer to the technical description.
GPIO1 General purpose digital input/output pin (interrupt available) or Analog input. For details, refer to the technical description.
SERIAL INTERFACE
RX UART receive data pin. Connect to TX pin of application processor.
TX UART transmit data pin. Connect to RX pin of application processor.
1WIRE 1-Wire bus interface. Open-drain signal that requires an external pullup resistor.
RTC
XIN 32.768kHz Crystal Input. Connect a 22pF load capacitance to ground.
XOUT 32.768kHz Crystal Output. Connect a 22pF load capacitance to ground.
32KHAP 32.768kHz Clock Output with internal 1.8V. Default ON in the low power mode. Connect to application processor
32KHO1 32.768kHz Clock Output with V32KHO1. The default is OFF.
32KHO2 32.768kHz Clock Output with V32KHO2. The default is OFF.
V32KHO1 IO power rail for 32KHO1 output.
V32KHO2 IO power rail for 32KHO2 output.
VCOIN Back up battery charger output. The default is 3.0V.
NO CONNECTION
NC Reserved pin for debug and/or future use. Do not connect to GND, VIN nor any other signal, otherwise the device could be permanently damaged
NC Reserved pin for debug and/or future use. Do not connect to GND, VIN nor any other signal, otherwise the device could be permanently damaged
NC Reserved pin for debug and/or future use. Do not connect to GND, VIN nor any other signal, otherwise the device could be permanently damaged
NC Reserved pin for debug and/or future use. Do not connect to GND, VIN nor any other signal, otherwise the device could be permanently damaged
NC Reserved pin for debug and/or future use. Do not connect to GND, VIN nor any other signal, otherwise the device could be permanently damaged
NC Reserved pin for debug and/or future use. Do not connect to GND, VIN nor any other signal, otherwise the device could be permanently damaged

External components

Rhomb uPMIC has internal inductors for all nine bucks, only external ceramic capacitors are required for power outputs.

Function PIN External

component

Notes Function PIN External

component

Notes
BUCK1 LINEAR REGULATORS
INB1 2.2µF 6.3V, X5R, Ceramic capacitor INL1 4.7µF 6.3V, X5R, Ceramic capacitor
BUCK1 4.7µF 6.3V, X5R, Ceramic capacitor INL2 4.7µF 6.3V, X5R, Ceramic capacitor
BUCK2 INL4 4.7µF 6.3V, X5R, Ceramic capacitor
INB2A 10µF 6.3V, X5R, Ceramic capacitor INL5 4.7µF 6.3V, X5R, Ceramic capacitor
INB2B 10µF 6.3V, X5R, Ceramic capacitor INL6 4.7µF 6.3V, X5R, Ceramic capacitor
BUCK2A 22µF 6.3V, X5R, Ceramic capacitor INL7 4.7µF 6.3V, X5R, Ceramic capacitor
BUCK2A 22µF 6.3V, X5R, Ceramic capacitor INL8 4.7µF 6.3V, X5R, Ceramic capacitor
BUCK3 INL9 4.7µF 6.3V, X5R, Ceramic capacitor
INB3 10µF 6.3V, X5R, Ceramic capacitor OUT1 1µF 6.3V, X5R, Ceramic capacitor
BUCK3 22µF 6.3V, X5R, Ceramic capacitor OUT2 2.2µF 6.3V, X5R, Ceramic capacitor
BUCK4 OUT3 1µF 6.3V, X5R, Ceramic capacitor
INB4A 10µF 6.3V, X5R, Ceramic capacitor OUT4 1µF 6.3V, X5R, Ceramic capacitor
INB4B 10µF 6.3V, X5R, Ceramic capacitor OUT5 1µF 6.3V, X5R, Ceramic capacitor
BUCK4A 22µF 6.3V, X5R, Ceramic capacitor OUT6 1µF 6.3V, X5R, Ceramic capacitor
BUCK4B 22µF 6.3V, X5R, Ceramic capacitor OUT7 1µF 6.3V, X5R, Ceramic capacitor
BUCK5 OUT8 1µF 6.3V, X5R, Ceramic capacitor
INB5 2.2µF 6.3V, X5R, Ceramic capacitor OUT9 1µF 6.3V, X5R, Ceramic capacitor
BUCK5 4.7µF 6.3V, X5R, Ceramic capacitor OUT10 2.2µF 6.3V, X5R, Ceramic capacitor
BUCK6 OUT11 1µF 6.3V, X5R, Ceramic capacitor
INB6 2.2µF 6.3V, X5R, Ceramic capacitor OUT12 1µF 6.3V, X5R, Ceramic capacitor
BUCK6 4.7µF 6.3V, X5R, Ceramic capacitor OUT13 1µF 6.3V, X5R, Ceramic capacitor
BUCK7 OUT14 1µF 6.3V, X5R, Ceramic capacitor
INB7 2.2µF 6.3V, X5R, Ceramic capacitor OUT15 1µF 6.3V, X5R, Ceramic capacitor
BUCK7 4.7µF 6.3V, X5R, Ceramic capacitor OUT16 1µF 6.3V, X5R, Ceramic capacitor
BUCK8 OUT17 2.2µF 6.3V, X5R, Ceramic capacitor
INB8 2.2µF 6.3V, X5R, Ceramic capacitor OUT18 1µF 6.3V, X5R, Ceramic capacitor
BUCK8 4.7µF 6.3V, X5R, Ceramic capacitor OUT19 1µF 6.3V, X5R, Ceramic capacitor
BUCK9 OUT20 1µF 6.3V, X5R, Ceramic capacitor
INB9 2.2µF 6.3V, X5R, Ceramic capacitor OUT21 2.2µF 6.3V, X5R, Ceramic capacitor
BUCK9 4.7µF 6.3V, X5R, Ceramic capacitor OUT22 2.2µF 6.3V, X5R, Ceramic capacitor
PERIPHERALS OUT23 2.2µF 6.3V, X5R, Ceramic capacitor
V32KHO1 0.1µF OUT24 1µF 6.3V, X5R, Ceramic capacitor
V32KHO2 0.1µF OUT25 1µF 6.3V, X5R, Ceramic capacitor
VCOIN 3.0V Coin battery or super-cap (3.0V typical) OUT26 1µF 6.3V, X5R, Ceramic capacitor
XIN 22pF 6.3V, COH, Ceramic capacitor SUPPLY
XOUT 22pF 6.3V, COH, Ceramic capacitor VIN 1µF 6.3V, X5R, Ceramic capacitor
XIN/XOUT XTAL 32.768kHz crystal, 12.5pF, 20ppm between XIN and XOUT

Electrical Characteristics

Test Conditions

Typical Values

The typical data are based on Tamb=25°C by simulation and/or technology characterisation unless otherwise specified.

Minimum and Maximum Values

The minimum and maximum values represent the worst conditions of ambient temperature, supply volt-age and frequencies, by simulation and/or technology characterisation unless otherwise specified

Absolute Maximum Ratings

The absolute maximum ratings are stress ratings, and functional operation under such conditions are not guaranteed. Stress beyond the limits specified in next table may affect the device reliability or cause permanent damage to the device. Functional operating conditions are given in General Operating Conditions section.

SYMBOL MIN MAX UNIT
VIN, INB1, INB2, INB3, INB4, INB5, INB6, INB7, INB8, INB9 to GND -0.3 +6 V
INL1, INL2, INL4, INL5, INL6, INL7, VCOIN, V32KHO1, V32KHO2 to GND -0.3 +6 V
INB1, INB2, INB3, INB4, INB5, INB6, INB7, INB8, INB9, ENB8, ENB9, LDOEN to GND -0.3 VIN + 0.3 V
PWREN, DVS1-3, SELB2, SELB3, SELB4, 32KHAP to GND -0.3 +2.1 V
RESET, RSTOUT, PWRON, #INT, #IRQ to GND -0.3 +2.1 V
RX, TX, 1WIRE, SPLCTRL, ADC, GPIO to GND -0.3 +2.1 V
BUCK1 to PGND1 -0.3 INB1 + 0.3 V
BUCK2A, BUCK2B,SNS2P to PGND2A/B -0.3 INB2 + 0.3 V
BUCK3, SNS3P to PGND3 -0.3 INB3 + 0.3 V
BUCK4A, BUCK4B,SNS4P to PGND4A/B -0.3 INB4 + 0.3 V
BUCK5 to PGND5 -0.3 INB5 + 0.3 V
BUCK6 to PGND6 -0.3 INB6 + 0.3 V
BUCK7 to PGND7 -0.3 INB7 + 0.3 V
BUCK8 to PGND8 -0.3 INB8 + 0.3 V
BUCK9 to PGND9 -0.3 INB9 + 0.3 V
OUT1, OUT6, OUT7, OUT8, OUT15 to GND -0.3 INL1 + 0.3 V
OUT5, OUT17 OUT18, OUT19 to GND -0.3 INL2 + 0.3 V
OUT3, OUT9, OUT11, OUT20 to GND -0.3 BUCK7 + 0.3 V
OUT4, OUT12, OUT21, OUT24 to GND -0.3 INL4 + 0.3 V
OUT10, OUT13, OUT14, OUT16 to GND -0.3 INL5 + 0.3 V
OUT22, OUT23, OUT25, OUT26 to GND -0.3 INL6 + 0.3 V
OUT2 to GND -0.3 INL7 + 0.3 V
XIN, XOUT to GND -0.3 +1.8 V
32KHO1 to GND -0.3 V32KHO1 + 0.3 V
32KHO2 to GND -0.3 V32KHO2 + 0.3 V
PGND1-9, SNS2N, SNS3N, SNS4N to GND -0.3 +0.3 V
BUCK1, 5, 6, 7, 8 & 9 Continuous RMS Current (Note 1) 1.5 A
BUCK2A, BUCK2B, BUCK3, BUCK4A, BUCK4B Continuous RMS Current (Note1) 2.5 A
Continuous Power Dissipation (TA = 70ºC) (Derate 33.3mW/°C above +70°C) 2670 mW
Operating Temperature Range -40 +85 ºC
Junction Temperature +150 ºC
Storage Temperature Range -65 +150 ºC
Soldering Temperature (reflow) +260 ºC

General Operating Conditions

TAMB

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
ISHDN Shutdown Supply Current VIN=4.2V, Backup battery is fully charged, all other functions OFF 6 20 µA
INO_LOAD1 No Load Supply Current 1 VIN=3.7V, BUCK1-9=ON (BUCK2, 3 & 4 in green mode), LDO1-26=ON, other functions off, backup battery is fully charged 490+? µA
BATT UNDERVOLTAGE LOCK-OUT
VUVLO_R Battery Undervoltage VIN rising -5% 3.0 +5% V
VUVLO_F Lockout Threshold VIN falling 2.25 V
THERMAL SHUTDOWN
TJSHDN Threshold, TSHDN TJ Rising, 15ºC hysteresis 165 ºC
TJ120 Thermal Interrupt 1 TJ Rising, 15ºC hysteresis 120 ºC
TJ140 Thermal Interrupt 2 TJ Rising, 15ºC hysteresis 140 ºC
LOGIC AND CONTROL INPUTS
VIL1 Input Low Level 1 PWREN, LDOEN, ENB8, ENB9, DVS1-3, SELB2-4, TA=25ºC 0.4 V
VIH1 Input High Level 1 PWREN, LDOEN, ENB8, ENB9, DVS1-3, SELB2-4, TA=25ºC 1.40 V
VIL2 Input Low Level 2 PWRON, #INT, GPIO, #RESET, RX, 1WIRE, TA=25ºC 0.54 V
VIH2 Input High Level 2 PWRON, #INT, GPIO, #RESET, RX, 1WIRE, TA=25ºC 1.26 V
VHYS Input hysteresis PWRON, #INT, GPIO, #RESET, RX, 1WIRE, TA=25ºC 0.11 V
VOL1 Output Low Level 1 , TA=25ºC V
VOH1 Output High Level 1 , TA=25ºC V
VOL2 Output Low Level 2 #IRQ,SPLYCTRL,TX,1WIRE,GPIO,#RSTOUT, TA=25ºC 0.5 V
VOH2 Output High Level 2 #IRQ,SPLYCTRL,TX,1WIRE,GPIO,#RSTOUT, TA=25ºC 1.3 V
VHYS Output hysteresis , TA=25ºC V
VRAM VDD voltage required to retain RAM 2.1 V
Logic Input LeakageCurrent
INTERNAL PULL-DOWN RESISTANCE
RPU Internal pull-up resistors PWRON, #INT, GPIO, #RESET to internal 1.8V 20 50
#SHTDN to VIN 56
RPD Internal pull-down resistors LDOEN, ENB8, ENB9 to GND 400 800 1600

System Faults

The uPMIC monitors the system for the following faults:

  • Global Thermal Fault
  • Local Thermal Shutdown
  • Under-Voltage Lock Out

Global Thermal Fault

Rhomb uPMIC has one centralized thermal circuit which senses temperature on the die. If temperature increases >165C (TSHDN) this constitutes a thermal shutdown event and the uPMIC enters its global shutdown state. In addition to the 165°C threshold, there are 2 additional comparators which trip at 120°C and 140°C. Interrupts are generated in the event the die temperature reaches 120°C or 140°C. There is a 15°C thermal hysteresis. After thermal shutdown, if the die temperature reduces by 15°C, the thermal shutdown bus is de-asserted and the default power-on supplies can be enabled in the sequencing again.

Local Thermal Shutdown

If any of LDOs or Step-down regulators reaches thermal shut down threshold, the uPMIC will shut down that block locally. If the temperature goes below a threshold, that block goes back to normal operation. The charger has an independent thermal control circuit that regulates die temperature during charging.

Under-Voltage Lock Out

When the power supply source, VIN, is below VUVLO , the uPMIC enters its under-voltage lockout mode (UVLO). The UVLO forces the uPMIC to a dormant state until the source voltage is high enough to allow the uPMIC to be securely functional. The UART does not function in UVLO and the UART type-O register contents are reset in UVLO. The rising UVLO threshold is set at 3.2V to turn on default-on power supplies

Power ON/OFF Events

Power ON/OFF timing diagram in the Initial Power-On Mode

Power ON/OFF timing diagram by PWREN in uPMIC=ON

Global ON/OFF Control by PWRON pin

Digital ON/OFF Control by PWREN pin

PWREN Signal

Once the Application Processor (AP) boots up, the AP is able to power down and up key core supplies and other voltage rails via PWREN signal to enter/exit (deep) sleep mode. PWREN status is ignored during initial power up and down processes. All programming must be done before the AP enterns the sleep mode by pulling PWREN low since the AP does not have programming capability in (deep) sleep mode.

For those BUCKs or LDOs that are controlled by PWREN, the on-sequence follows the same on-sequence at initial start-up mode, except for some regulators. The default ON sequence is as follows.


Control Scheme for BUCK1-4 by PWREN pin

All Buck1-4 have independent UART enable bits and external enable pin (PWREN). As shown in the figure below bits are logically ORed with the PWREN. The PWREN is typically connect to the dedicated pin on the Application Processor.


Following is an example on how to control BUCK4 by the PWREN. Example, once AP is booted up and running:

  1. Start the programming via UART (writing to BUCK4 UART registers)
  2. Attach the BUCK4 to PWREN-dependant control

Control Scheme for LDOs by PWREN pin

For LDO2,6,7,8,10,11,12,14,15 and 16 have independent UART enable bits and hardware enable pins (PWREN). As shown in the figure below bits are logically ORed with the PWREN. The PWREN is typically connect to the dedicated pin on the Application Processor.


Digital ON/OFF Control by LDOEN pin

LDO20, LDO21 and LDO22 have a common external pin, LDOEN, to enable/disable the output of all said LDOs at a time. The control of enabling the LDOs is OR gate by either UART=ON or LDOEN=High. Refer to the registers for the details.

Register Power-On Reset (POR)

Power-On Reset (POR) occurs by any power-off events. This shutdown causes #RSTOUT=LOW. This condition resets all previously programmed values in the O-Type registers to their POR value. But, all S-type registers are only reset when VCOIN are below its UVLO threshold.

Reset Output (#RSTOUT) Assertion and De-Assertion

In the initial power-on sequencing, a 60ms reset timer is started after PWRON=Low. At the completion of the 60ms reset timer, #RSTOUT goes high (based on no other circuit pulls low on this WIRED-OR output). After #RSTOUT is asserted high; the default-on supplies will be maintained ON. Note that PWRON must be set to an appropriate status until PWRHOLD is able to keep all default-on regulators on in the initial power-on mode.

Manual Reset Function on (#RESET)

By default, pin #RESET is the hard manual reset pin to reset system in normal operating mode. This pin has an internal pull-up of 30k. If #RESET=Low the uPMIC will reset and a new automatic power-On sequence will be started. Note that #RESET must be released in order to uPMIC exits from reset state and to start the new automatic power-On sequence.

If not used, this pin can be re-configured to act as an extra GPIO (GPIO4) with following features:

  • GPIO4 can be configurable as general purpose digital input/output with interrupt available and internal pull-up/pull-down (not configurable as analog input)

Manual Reset Function using #PWRON button

Current Mode BUCK Converters, BUCK2, 3 & 4

Feature

  • 32µA Quiescent Current in Normal Mode (BUCK2 & 4)
  • 16µA Quiescent Current in Normal Mode (BUCK3)
  • 5µA Quiescent Current in Low-Power Mode
  • 5A with differential remote sense (BUCK2 & 4)
  • 2.5A with differential remote sense (BUCK3)
  • Small 1.0µH Inductors
  • No External MOSFETs, Synchronous Rectifiers or Current Sense Resistors are Required
  • Dynamically Programmable Output Voltage
  • Programmable Output Voltage Slew Rate during dynamic voltage changes.
  • Low-Power Mode Increases Light-Load Efficiency
  • Forced PWM Operation Selectable through Serial Interface
  • Remote Output Voltage Sensing
  • ±1% Steady-State Accuracy
  • Soft-Start into Pre-Biased Output

Details Description

The uPMIC features two ultra-low I Q step-down regulators. In normal operation, BUCK2 & 4 step-down regulators consume only 32µA of quiescent current while BUCK3 consumes 16µA of quiescent current. In standby mode, the quiescent current is reduced to 10µA per step-down regulator.

Each step-down regulator can be independently put into standby mode by writing a bit in a control register. Each step-down regulator provides internal feedback, minimizing external component count by allowing all step-down regulator output voltages to be programmed through the serial interface. These three step-down regulators feature dynamic voltage scaling through (DVS3/2/1) through the external DVS3/2/1 and SELB4/3/2 interface. Additionally, these three step-down regulators automatically transition from PFM to PWM operation (FPWM=0). Forced PWM operation can be independently enabled for each step-down regulator by setting FPWM. Each phase of BUCK2 and 4 is interleaved.

Soft-Start

The step-down regulators have a soft-start rate of 25mV/us (dV/dt). When a step-down regulator is enabled, the output voltage ramps to its final voltage with a slew rate of 25mV/us. The controlled soft-start rate and the step-down regulator current limit (I LIMP ) limit the input inrush current to the output capacitor (I INRUSH ). I INRUSH =min(I LIMP & C OUT *dV/dt). Note that the input current on the step-down converter will be lower than the inrush current to the output capacitor by the ratio of output to input voltage.

The step-down regulators support starting into a pre-biased output. For example, if the output capacitor has an initial voltage of 0.4V when the regulator is enabled, the regulator gracefully increases the capacitor voltage to the required target voltage such as 1.0V. This is unlike other regulators without the start into pre-bias feature where they may force the output capacitor voltage to 0V before the soft-start ramp begins.

Example: What is the inrush current when starting BUCK2 with an output capacitance (COUT ) of 22uF?

  • IINRUSH = min (ILIMP & COUT * dV/dt)
  • BUCK2 is a two phase regulator with a typical PMOS current limit (ILIMP) of 3.75A per phase. For ILIMP in the above equation we will use 2 x 3.75A = 7.5A
  • BUCK2 has a typical soft-start rate (dV/dt) of 25mV/us. For dv/dt in the above equation we will use 25mV/us.
  • IINRUSH = min (7.5A & 22uF*25mV/us)
  • IINRUSH = min (7.5A & 0.55A)
  • IINRUSH = 0.55A

Dynamic Voltage Scaling (DVS)

Buck 2, 3 and 4 include DVS feature that allows each output voltage to change dynamically. The Buck 2 and 4 output voltage is selected by DVS1-3 and SELB2/4. See the table below.


To have a specific voltage in the DVS mode, both DVS3/2/1 and SELB2/3/4 need to be set accordingly. In the initial power on Mode, the output on these three regulators is set by each BUCK_DVS1 register since all DVS3/2/1 stay at low. In order to have a pre-set output in DVS scheme, the SELB_ must be set to Low. If this stays low, a previous set voltage is only valid on each regulator.

Remote Output Voltage Sensing (ROVS)

BUCK2/3/4 feature remote output voltage sensing (ROVS) for improved output voltage accuracy. The SNSxN and SNSxP inputs connect directly across the load, with the SNSxN pin connected to a quiet analog ground near the load, and SNSxP connected directly to the load’s power input. The ROVS can be independently disabled through software in order to reduce quiescent current consumption (ROVS_EN_Bx). Disabling the ROVS reduces the quiescent current consumption.

When BUCK2/3/4 is placed in low power mode, the ROVS is automatically disabled. Although the ROVS is automatically disabled, the ROVS_EN_Bx bits are not be automatically cleared. If ROVS_EN_Bx is set when BUCK2/4 enters normal power mode, the ROVS feature will automatically re-enable.

Inductor

BUCK2 and 4 operate with two internal 1.0uH inductors and BUCk3 operates with one internal 1.0uH inductor.


Input Capacitor Selection

The input capacitor, CIN, reduces the current peaks drawn from the battery or input power source and reduces switching noise in the IC. The impedance of CIN at the switching frequency should be kept very low. Ceramic capacitors with X5R or X7R dielectrics are highly recommended due to their small size, low ESR, and small temperature coefficients. For most applications a 10µF capacitor is sufficient.

Output Capacitor Selection

The output capacitor, COUT, is required to keep the output voltage ripple small and to ensure regulation loop stability. COUT must have low impedance at the switching frequency. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. Due to the unique feedback network, the output capacitance can be very low. The recommended values are summarized in the following table.

Regulator Capacitance
BUCK2 2 x 22µF
BUCK3 22µF
BUCK4 2 x 22µF

Efficiency Graphs on Buck2,3,4

Hysteresis BUCK Converters, BUCK1,5,6,7,8 & 9

Feature

  • 25µA Quiescent Current in Normal Mode
  • 1.5A for BUCK1, 5, 6, 7, 8 & 9
  • Internal 1.0µH Inductor on all BUCKs
  • No External MOSFETs and Synchronous Rectifiers are Required
  • Forced PWM Operation Selectable through Serial Interface
  • ±3% Steady-State Accuracy
  • Soft-Start

Inductor

BUCK2 and 4 operate with two internal 1.0uH inductors and BUCK3 operates with one internal 1.0uH inductor.


Output Capacitor Selection

The output capacitor, COUT, is required to keep the output voltage ripple small and to ensure regulation loop stability. COUT must have low impedance at the switching frequency. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. Due to the unique feedback network, the output capacitance can be very low. The recommended values are summarized in the following table.

Regulator Capacitance
BUCK1 4.7µF
BUCK5 4.7µF
BUCK6 4.7µF
BUCK7 4.7µF
BUCK8 4.7µF
BUCK9 4.7µF

Efficiency Graphs on Hysteresis Bucks

Linear Regulators

Feature

  • 22µA Quiescent Current in Normal Mode (LDO2)
  • 20 µA Quiescent Current in Normal Mode (300mA LDOs)
  • 18 µA Quiescent Current in Normal Mode (150mA LDOs)
  • 1µA Quiescent Current in Low Power Mode
  • Soft-Start
  • Low Drop-Out Voltage, 50mV typ at full load

Control Scheme for the LDOs by PWREN

For LDO2,6,7,8,10,11,12,14,15 and 16 the uPMIC has independent UART enable bits and hardware enable pin (PWREN). As shown in the figure below bits are logically ORed with the PWREN. The PWREN is typically connected to Application Processor’s GPIO.


Control Scheme for non-PWREN LDOs

For LDOs LDO1,3,4,5,9,13,17,18,19,20,21,22,23,24,25,26 that are not ON/OFF by PWREN, the logic table is as below.

BIT Name Description
7:6 OPMODE 00: OFF, except LDO3. LDO3 is always ON.

01: ON in Low Power Mode

10: Output ON with Low Power Mode by PWREN

  PWREN=H (1) : Output ON in Normal Mode 
  PWREN=L (0) : Output ON in Low Power Mode 

11: ON in normal mode

The LDO20, LDO21 and LDO22 with the external pin LDOEN

LDO20, LDO21 and LDO22 have a common external pin, LDOEN, to enable/disable the output of all said LDOs at a time. The control of enabling the LDOs is OR gate by either UART=ON or LDOEN=High. Refer to the registers for the details.

BIT Name Description
7:6 OPMODE 00: OFF (when LDOEN is Low)

01: ON in Low Power Mode

10: Output ON with Low Power Mode by LDOEN

  LDOEN=H (1) : Output ON in Normal Mode,
  LDOEN=L (0) : Output ON in Low Power Mode 

11: ON in normal mode

Low Power Mode

Each regulator includes a low-power mode where the quiescent current drop to only 1µA.

Soft-Start and Dynamic Voltage Change

When a regulator is enabled, the output voltage ramps to the final voltage at the slew rate of 100mV/µs. The 100mV/µs ramp rate results in around 220mA inrush current with a 2.2µF output capacitor and no load, but achieves regulation within 50µs. The soft-start ramp rate is also the rate of change at the output when switching dynamically between two output voltages without disabling.

Active-Discharge

Each LDO regulator has an active-discharge resistor that can be enabled/disabled with the ADSLDOxx bit. This is enabled by default. Enabling the active discharge feature helps ensure a complete and timely power down of all system peripherals. The default condition of the active-discharge resistor feature is enabled such that whenever VIN is below its UVLO threshold all regulators will be disabled with their active discharge resistors turned on.

Overvoltage Clamp

Each LDO has an overvoltage clamp that allows it to sink current when the output voltage is above its target voltage. This overvoltage clamp is default enabled but can be disabled with LxxOVCLMP_EN.

Adjustable Compensation

All PDRV LDOs that have a remote capacitor have adjustable compensation. This feature can be used to adjust the compensation of the LDO based on the resistance and inductance to the remote capacitor. This ability will allow each LDO to be programmed for optimal load transient performance based on the location of its remote capacitor. Please refer to the Control Register for more details. The LDO compensation should be switched only when that LDO is off. If the compensation switches when the LDO is enabled, it will cause unknown output glitches, due to switching in uncharged capacitors (as compensation changes).

PCB Layout Guidelines

DC Power Distrbution Guidelines

Use wide traces for power supply lines. Use a multi plated VIA holes to connect power supply traces between layers.

PCB Trace Width vs. Current and Length

Adequate trace or fill area width is needed to limit the IR drop as current is routed across the board. An IR drop of 1% or less is strongly recommended between the regulator outputs and their loads. The typical way to calculate a minimum trace width is described below;

  1. Deterine the maximum load current (Iload_max)
  2. Know the regulator‟s target output voltage(Vout)
  3. Calculate the maximum tolerable trace resistance (Rpcb_Max) assuming a 1% IR drop. Rpcb_Max=(0.01 x Vout) / Iload_max
  4. determine accurate trace length (L) and the copper thickness (T); 1 ounce copper foil thickness is 1.34mil.
  5. Calculate the minimum trace width (W) as
    • W = (p x L) /(Rpcb_max x T)
    • where; p = the resistivity of copper (1.7 x 10 -8 ohm-m)

Guidelines for BUCK converters

Hyesteresis Buck Converter

All Hyesteresis buck converers on uPMIC have an external input and external output capacitor, and internal inductor. The external capacitors must be placed in a right location to maximize the performance. To maximize the performance, two example PCB layouts for BUCK8 are depicted as below;

  • The loop (1) is the most important in layout design. In order to reduce the loop impedance, place the input capacitor closer to the uPMIC Pins (PGND and INB_ ).
  • Feedback line does not have to be a thick trace.
  • Connect the feedback line (Buck8) to the end of load.
  • Place each output capacitor near its corresponding input capacitor to share a common layer ground.
  • Use a thick trace for the main high current paths.


Current Mode Buck Converter

To maximize the buck performance, an example of PCB layout for Buck2 is depicted below.

  • The loop (1) is the most important in layout design. In order to reduce the loop impedance, place the input capacitor closer to the PMIC Pins (PGND and INB_ ).
  • Feedback line does not have to be a thick trace.
  • Connect the sense + and - lines to the end of load.
  • Place each output capacitor near its corresponding input capacitor to share a common layer ground.
  • Use a thick trace for the main high current paths.


BACK-UP CHARGER

Features

  • 800uA maximum CC-CV back up battery charger.
  • 2.5V – 3.5V adjustable back up battery setting with ± 3% Tolerance

Description

The Back-up battery charger remains ON as long as there is a valid power input source on VIN and BBCHOSTEN bit is set to 1. The backup battery charger is a voltage limited current source with a default 1kΩ output resistor. Backup Charger has an UART adjustable output voltage in 2.5V, 3.0V, 3.3V, or 3.5V with 3.0V as the default output voltage. The power up default is ON. See the register section for details on how to adjust the output voltage.

32KHz CRYSTAL OSCILLATOR

uPMIC oscillator consists of a crystal driver with an external load capacitance. When the crystal driver is enabled, it starts up in low power mode, drawing only 1.5uA of current. The Lowjittermode bit controls the crystal driver in either low power mode or low jitter mode (high power mode). When the LowJittermode bit is set to 1, low jitter mode on three channels is activated at the same time. In the low-jitter mode, the current consumes about 30uA typically. In worse case, this current goes up to 50uA.

These three 32khz buffer outputs (32KHAP, 32KHO1, 32KHO2) are independently enabled/disabled over UART. However, the low-jitter mode on each output can not be applied. The crystal driver is supplied from the internal VRTC node which is equal to VIN if VIN > 2.55V otherwise VRTC is equal to VCOIN.

The crystal driver will generate three channel 32k buffered outputs. The 32KHAP output is normally routed to the AP Processor. The other two outputs (32KHO1, 32KHO2) are intended for the BT, WLAN, BB or peripheral chipsets. The 32KHAP has a supply voltage of internal always ON 1.8V, while 32KHO1 and 32KHO2 supply voltage are provided by V32KHO1 and V32KHO2 respectively.


#IRQ PIN Description

The Rhomb uPMIC uses the Interrupt pin, #IRQ, to indicate to the application processor that the status on the uPMIC has changed. The #IRQ signal is asserted whenever one or more interrupts are toggled. The application processor shall read the interrupt source register to see the source of interrupt event. If the bit 0, RTC, in the register, INTSRC 0x01, is asserted high, it indicates the source of interrupt event from RTC section. In this moment, application processor should read the RTC interrupt register, RTCINT, 0x00.

Each Interrupt register can be read at a time. The #IRQ pin becomes high (cleared) as soon as the read sequence finishes. If an interrupt is captured during the read sequence, the #IRQ pin will become active (low) after minimum 1ms. All interrupts can be masked to prevent the #IRQ from being asserted for masked interrupts. A mask bit in the INTxMSK registers implements masking.

The INT1 register can still provide the actual interrupt status of the masked interrupts. If the mask bit is cleared for an active interrupt, the IRQ goes low at the next falling edge of the 32KHz-clock output.


RTC Functional Description

This Real-time clock (RTC) is responsible for keeping track of the time. It records seconds, minutes, hours, days, months and years with a calendar structure that accounts for leap years. The RTC is further equipped wit two alarms and has a host of interrupt capabilities.

Through a set of control registers various modes of operation are possible. RTC supports both “Binary”, and “Binary Coded Decimal”, and supports features such as AM/PM, 24/12 modes of operation. Additional sudden momentary power loss (SMPL) and watchdog timeout and software reset (WTSR) are available.

Write/Read Operation

Before proceeding further, we need to get familiar with how a write to and a read from RTC is going to occur. The user uses UART to interface with RTC registers. However, the UART and RTC operate in totally asynchronous clock domains.

For example, while UART may operate at 115200bauds, the main clock runs at 32.768 kHz. In addition to the fact that meta-stability may be introduced during a read or a write operation, other side effects such as a read error could occur. A read error may be observed when reading a single timing register (such as a SECOND register) as the register is changing its value. The other read error possibility occurs when reading multiple registers (such as a MINUTE and SECOND registers together) and one register value changes between the reads (such as SECOND register changing after it is already been read and the user is in process of reading the MINUTE register).

Therefore, it is needed to make sure that both writing to and reading from RTC happens as reliably as possible. For this reason, two sets of independent buffers “Write Buffers”, and “Read Buffers” are implemented which are used for writing to and reading from RTC.

Writing to RTC

In order to safely write to various registers on-board the RTC, all RTC registers (except RTCINT register, bit 0 and 4 of UPDATE0 Register) have a corresponding “Write Buffer”. When the user writes to the RTC, the user is actually performing a write to these “Write Buffers”. Therefore, in writing to RTC there are 2 steps needed to update a particular register or set of registers: 1. User writes desired value(s) to the register(s) located between 0x01 and 0x24. Behind the scene, only the “Write Buffers” are updated with these new values. 2. The user then writes a 1 to UDR bit 0 of the “UPDATE0 Register” at address 0x04 to transfer the modified “Write Buffers” to the corresponding time registers.

The logic subsequently would perform a transfer of data from Write Buffers to the actual registers and then clears the “UDR” bit automatically as well as clearing the Write Buffers (marking them as not modified). The user then has to either poll the UDF “UPDATE Flag” bit (bit 0 of UPDATE1 register), or rely on the interrupt to initiate a new write operation (The UDF is set to 1 as soon as the write operation occurs).

Pseudo code for setting clock to Saturday, Jan 01, 2011, 1:00:00 PM

Set RTCCNT to 0x01 //12hr mode, BCD mode Set RTCSEC to 0x00 // 0 second Set RTCMIN to 0x00 // 0 minute Set RTCHOUR to 0x41 // 1 PM Set RTCDOW to 0x40 // Saturday Set RTCMONTH to 0x01 // January Set RTCYEAR to 0x11 // 11 Set RTCDOM to 0x01 // First Set RTCUPDATE0 to 0x01 // transfer write buffers to counters Loop: Read RTCUPDATE1 If UDF is 0 then go back to Loop //wait until UDF is set before initiating new write

Set RTCSEC to 0x… //new write

Pseudo code for setting ALARM1 to every Wednesday at 7:30:00 AM

Set RTCCNT to 0x01 //12hr mode, BCD mode Set RTCSECA1 to 0x80 //0 sec, enabled Set RTCMINA1 to 0xB0 //30 minute, enabled Set RTCHOURA1 to 0x87 //7 AM, enabled Set RTCDOWA1 to 0x08 //Wednesday, enabled Set RTCMONTHA1 to 0x00 //Disabled Set RTCYEARA1 to 0x00 //Disabled Set RTCDOMA1 to 0x00 //Disabled Set RTCUPDATE0 to 0x01 // transfer write buffers to counters Loop: Read RTCUPDATE1 If UDF is 0 then go back to Loop //wait until UDF is set before initiating new write

Set RTCSEC to 0x… //new write

Under the hood, the logic first does a double synchronization of the UDR bit to the 32.768 kHz clock before using it as an enable bit (UDR_sync in figure 1) to transfer from Write buffers to the actual registers thus allowing a safe update of these 2 unsynchronized clock events

Reading from RTC

Corresponding to most timing registers there are a series of “Read Buffers”. In order to safely read from various registers on-board the RTC, all RTC registers (except RTCINT register and bit 0 and 4 of UPDATE0 Register) have a corresponding “Read Buffer”. When the user reads from the RTC, the user is actually performing a read from these “Read Buffers”. Therefore, there are 2 steps needed to read a particular register or set of registers:

  1. 1. The user writes a 1 to RBUDR bit 4 of the “UPDATE0 Register” at address 0x04 to transfer the most timing registers to “Read Buffers”. Behind the scene, the “Read Buffers” are updated.
  2. 2. The user then reads from the desired register location.

After step 1, the logic subsequently would perform a transfer of data from the actual registers to the “Read Buffers” and then clears the “RBUDR” bit. The user then has to either poll the RBUDF “UPDATE Flag” bit (bit 1 of FLAG register), or rely on the interrupt to initiate a new write operation (The RBUDF is set to 1 as soon as the transfer operation occurs).

Pseudo code for reading the time:

Set RTCUPDATE0 to 0x10 // transfer timekeeper counters to read buffers Loop: Read RTCUPDATE1 If RBUDF is 0 then go back to Loop //wait until UDF is set before initiating new write Read RTCSEC // second Read RTCMIN // minute Read RTCHOUR // hour Read RTCDOW // Day of Week Read RTCMONTH // Month Read RTCYEAR // Year Read RTCDOM // Day of Month

Pseudo code for reading ALARM1 setting

Set RTCUPDATE0 to 0x10 // transfer timekeeper counters to read buffers Loop: Read RTCUPDATE1 If RBUDF is 0 then go back to Loop //wait until UDF is set before initiating new write Read RTCSECA1 //sec Read RTCMINA1 //minute Read RTCHOURA1 //hour Read RTCDOWA1 // Day of Week Read RTCMONTHA1 // Month Read RTCYEARA1 // Year Read RTCDOMA1 // Day of Month

Under the hood, the logic first does a double synchronization of the RBUDR bit to the 32.768 kHz clock before using it as a clock to transfer from the actual registers to the “Read Buffers” thus allowing a safe update of these 2 unsynchronized clock events.

INPUT/OUTPUT

Rhomb uPMIC has three configurable pins (GPIO0, GPIO1 and GPIO2) reserved for user use. They can be configured as follows:

  • GPIO0 can be configurable as general purpose digital input/output (interrupt available and internal pull-up/pull-down resistor) or as analog input.
  • GPIO1 can be configurable as general purpose digital input/output (interrupt available and internal pull-up/pull-down resistor) or as analog input.
  • GPIO2 can be configurable as general purpose digital input/output (with internal pull-up/pull-down resistor, no interrupt available), as analog input or as 1-WIRE serial interface.

1-WIRE

When GPIO2 is configured as 1-WIRE serial port, Rhomb uPMIC can read/write from/to an external 1-wire EEPROM memory in order to read/store one or more automatic power-On sequences.

By default, only one power-On sequence is stored in internal memory, with its configuration data flashed in factory and not modifiable by UART. When an external 1-wire EEPROM is used then one or more additional automatic power-On sequences can be defined by the user. In this case, the configuration data for any extra power-On sequence can be sent by UART interface. Once the uPMIC receives the configuration data by UART it writes it to the external 1-wire EEPROM. After doing so the user can indicate the uPMIC which automatic power-On sequence should be used after any new power-On/reset event.

  • The configuration data for power-On sequence can also be directly flashed on external 1-wire EEPROM (in or off-system flashing). This allows to set different power-On sequences for different products just by changing the external EEPROM memory.

PWRHOLD Function

Any of available GPIOs, GPIO0-3, can be configured to act as PWRHOLD pin. When configured for it, this pin must be activated (HIGH level) by the AP (application processor) in order to indicate to uPMICC that the system has started-up OK and that uPMIC must hold all configured power outputs ON.

When a GPIO is configured as PWRHOLD, then after a power-On event the uPMIC starts checking the PWRHOLD pin after a debounce delay time and it keeps checking it all the time.

  • If PWRHOLD=High after delay time then the uPMIC will hold all configured power outputs ON
  • If, at any time, PWRHOLD=Low then the uPMIC will shutdown all power outputs

Analog Input

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UART Serial Interface

An UART serial interface is used for regulator on/off control, setting output voltages, and other functions. See section ‘UART Register Map’ for the complete register map.

Communication Speed

By default, the UART serial interface works at 115.200 bauds. This speed can be changed by the user